Programmable Device Circuits and Systems

V. Kavitha ¹, V. Kannan ²

Affiliations
1 Department of Electrical and Electronics Engineering (ECE) in Dr. MGR Educational and Research Institute, Chennai–600095, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu, IN

Abstract

Shared resource problem arises in realtime applications due to the lack of mutual exclusiveness of resource for a task that leads to data corruption and contention. This paper implements kernel activity schemes for effective handling of multiple tasks using RTOS concepts to suit critical applications and concurrent task handling in realtime environment. To protect shared data and to achieve task synchronization, schemes of interrupt enabling/disabling and global variable usage are employed using Priority based Preemptive Task scheduling algorithm in uc/os-II Real Time Operating System on cortex M3 processor. This algorithm is optimum with respect to task execution time and interrupts response. The resultant empirical evidence demonstrates improvement of system performance and response under critical activities.

Keywords

Critical Section, Micro/os-II, Priority Scheduling Shared Data Problem, UML Diagram.

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A. Nandhini ¹, V. Kannan ², E. Logashanmugam ¹, B. Sheela Rani ¹, Raju Daniel ³

Affiliations
1 Sathyabama University, Sholinganallur, Chennai, Tamilnadu, IN
2 Jeppiaar Institute of Technology, Kunnam, Kanchipuram District, IN
3 Institute of Plasma Research, Bhat, Gujrat, IN

Abstract

A stable integrator of long duration up to 5s has been designed for Aditya tokamak. In tokamaks, the accurate knowledge about the plasma position has been required for maintaining the distance between plasma and in vessel component. Hence, the value of plasma current, magnetic field and magnetic flux are to be calculated by integrating signals from the magnetic pick up loops. High accuracy integrators are required for the accurate magnetic measurements for long duration signals. The proposed integrator design composed of microcontroller, DAC, integrator and ADC. This design provides a stable output for noisy and drift input signal level up to 5s. The microcontroller has been used to maintain the stability of the output signal and also eliminate the offset induced noise components.

Keywords

ADC, Drift, Integrator, Microcontroller, Plasma.

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N. Marie Claude ¹, N. Marie Wilson ², V. Kannan ³

Affiliations
1 IFET College of Engineering, Villupuram-605108, Tamil Nadu, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai-631 604, IN
3 Jeppiaar Institute of Technology, Sriperumpudur, Chennai-631604, IN

Abstract

This work demonstrates the application of PVDF/CNT composite as strain sensor and defect detector. The PVDF/CNT films were prepared by solution/filtration method and were bonded directly onto specimens by nonconductive adhesive. The two electrodes were connected on to PVDF/CNT films with silver conducting epoxy to reduce contact resistance. Conventional Strain gauge is also attached to other end of the specimen for comparison. For testing purpose 9CR 1MO material is considered and cut into dog bone shaped structures according to ASTM standards. Tensile load is applied by subjecting the specimen in a servo hydraulic test frame .Calibration curves were plotted with change in voltage versus the strain obtained in test specimen. The result shows that there is linear change in voltage across the film when subjected to tension. The defect detection is done using electronic measurement technique. The results shows that the presence of defect was marked by high value of resistance on that particular region and the resistance value was low in non-defective region.

Keywords

Carbon Nanotubes (CNT), Polyvinylidenefluoride (PVDF), Composite Films, Strain Sensor, Defect Detection.

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V. Nagarajan ¹, V. Kannan ²

Affiliations
1 SASTRA University, Thanjavur, IN
2 Jeppiaar Institute of Technology, Sriperumpudur, Chennai, IN

Abstract

This paper identifies and resolves the weakness and limitation of existing Cellular Automata (CA)-based byte Error Correcting Code (ECC) and proposes an improved CA-based multi byte ECC which overcomes the identified weakness up to some extent. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed–Solomon (RS) Codes. In this paper we are designing the Cellular Automata (CA) based multi byte error correction architecture. Cellular Automata is established for developing bits and bytes Error Correcting Codes. This code is very much suited from Very Large Scale Integration design viewpoint and requires much less hardware and power for decoding. The existing CA based error correcting scheme explains only about the double byte error correction. But this paper explains the error correction possibilities even if more than two errors present.

Keywords

Cellular Automata, Error Correcting Code, Multi Byte ECC.

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G. Prabhakaran ¹, V. Kannan ¹

Affiliations
1 Sathyabama University, Chennai-600118, Tamilnadu, IN

Abstract

 A new technique is presented in this paper for the design of a Hybrid TFT operational amplifier made by morphous Silicon thin film transistor and MOSFET which operates at 3V power supply. The OPAMP designed is a two-stage Hybrid TFT OPAMP followed by an output buffer. This Operational Amplifier employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. As compared to the conventional approach, the proposed hybrid operational amplifier result in a higher unity gain amplifier under the same load condition. In this paper we analyze the results of non-inverting amplifier, inverting amplifier, differential amplifier, differentiator and integrator of hybrid operational amplifier, using simulation with Integrated Circuit Emphasis (HSPICE).

Keywords

Operational Amplifier, Hybrid, Non-Inverting Amplifier, Inverting Amplifier, Differential Amplifier, Differentiator, Integrator, Amorphous Silicon Thin Film Transistor, MOSFET, Simulation, HSPICE.

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T. Jaya ¹, V. Kannan ²

Affiliations
1 Sathyabama University, Chennai, IN
2 VLSI Dept, Sathyabama University, Chennai, IN

Abstract

Analytical model for transconductance ac characteristic of buried-gate GaAs MESFET has obtained by solving continuity equation. When optical fiber is inserted into the active layer of buried-gate GaAs MESFET, the modulated light with frequency is 0.1GHz and Photon absorption coefficient (α) = 1.0x106 m-1 are applied to the buried gate GaAs MESFET through the optical fiber without any deviation. The drain current has calculated from that transconductance is noted. Drain-source current has calculated from the mobility of carriers and absorption coefficient of light. The mobility of the carrier controls the transconductance. The number of holes crossing the Schottky junction calculates the photo voltage. The transconductance and photo voltage characteristic indicate very good performance of the device compared to other devices like MESFET under back illumination and MESFET with front illumination having surface gate. It is highly use full in the nanotechnology and high-speed device.

Keywords

Gallium Arsenide Optical Field Effect Transistor GaAs OPFET, Metal Field Effect Transistor (MESFET), Optical Field Effect Transistor (OPFET).

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V. J. K. Kishor Sonti ¹, V. Kannan ²

Affiliations
1 Sathyabama University, Chennai 600119, IN
2 Department of VLSI Design, Sathyabama University, Chennai 600 119, IN

Abstract

In this paper a comparative analysis of effect of noise in MODFET and MESFET was carried out. Noise is inherent in the device because of various reasons such as leakage current, drifting of charge carriers randomly in the drift space and also because of the charge transportation. There are different kinds of noise which affect the performance of the devices at low and higher frequencies. In this paper, the effect of noise at the input and output of MODFET and MESFET w.r.t to frequency is analyzed. Results are analyzed at 3GHz and 9GHz, because the influence of shot noise will be higher at higher frequencies, whereas flicker noise is higher at lower frequencies. Results show that the effect of noise is more on the MESFET when compared with the MODFET. The effect of noise on the drain characteristics of modfet is also analyzed, where the maximum drain current without the influence of the noise is observed to be 130mA, whereas under the influence of noise, it is observed as 15uA. The work is carried out using PSPICE AD of Orcad 9.1.

Keywords

Drain Current, Equivalent Circuit, MODFET, MESFET, Noise.

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T. Ravi ¹, V. Kannan ²

Affiliations
1 Sathyabama University, Chennai, Tamilnadu-600119, IN
2 Department of VLSI Design, Sathyabama University, Chennai, Tamilnadu, 600119, IN

Abstract

This paper enumerates the efficient design and analysis of shift registers like Serial in serial out (SISO), Serial in Parallel out (SIPO), Parallel in parallel out (PIPO), Parallel in serial out (PISO) using N-type CNTFET Single Edge Triggered D Flip-flop. The Flip flop is designed using Ballistic CNTFET (VHDL-AMS model) with the diameter of cnt is 1nm in resistive load inverter logic. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by considering the carbon nano tube have promising application in the field of electronics. The transient and power analysis are obtained with operating voltage at 0.6V for the single edge triggered D flip-flop and shift registers using system vision tool. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The power consumption of D-Flipflop using mosfet has 9.136uw, whereas for the cntfet based design it was obtained as 0.15uw. Similarly when the shift registers were designed using cntfet power consumption values are 60% better than that of mosfet designs. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.

Keywords

CNT, CNTFET, Single Edge Triggered D Flip Flop, Shift Registers, Design Constraints, Circuit Simulation.

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V. Kannan ¹, V. Vijayakumar ¹, P. E. Sankaranarayanan ¹, S. K. Srivatsa ²

Affiliations
1 Sathyabama University, Chennai-600118, Tamilnadu, IN
2 St.Josephs Engineering College, Chennai-600118, Tamilnadu, IN

Abstract

The DC performance of depletion mode AlGaAs/GaAs MODFET under backside optical illumination is studied. A device structure with fiber inserted into the substrate upto the GaAs layer is considered for direct illumination into the GaAs layer. The AlGaAs layer is considered transparent to illumination. The photoconductive effect and the internal reflection effect which increase the 2DEG channel electron concentration are considered. These free electrons generated in the GaAs layer due to both photoconductive effect and the internal reflection effect are collected in 2DEG, there by increasing the source to drain current. The photo generated holes in GaAs layer drift towards the semi-insulating substrate and are capacitively coupled into the grounded source. The sheet concentration , I-V characteristics, transconductance and transfer characteristics of the device AlGaAs/GaAs MODFET have been evaluated and discussed. The I-V characteristics is compared with available experimental data at a particular gate source voltage with and without illumination.

Keywords

Optical Illumination, MODFET, Sheet Concentration, Transconductance, 2DEG.

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V. Saravanan ¹, V. Kannan ¹

Affiliations
1 Sathyabama University, Chennai, IN

Abstract

Carbon Nanotube Field Effect Transistors (CNTFET) are new nano-scaled devices to replace the MOSFET in nano-scale range to provide high performance, very dense and low power circuits. Small size of the MOSFET, below a few tens of nanometres creates the low Trans-conductance, gate oxide leakage, low ON-current, Mobility degradation and increased delay. Problems observed in the MOSFET when size is reduced are avoided in CNTFET, In case of CNTFET carbon nanotube is used as channel and high-k material is used as gate dielectric. In this paper, we present the simulation results of semi-conducting Carbon Nanotube Field Effect Transistors based logic gates and SR Flip Flop. The simulation is done using HSPICE and the current conduction of CNTFET is also analysed.

Keywords

Carbon Nanotube, CNTFET, NAND Gate, SR Flip Flop.

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